1. Field of the Invention
The present invention relates to a metal-insulation semiconductor (MIS) transistor circuit. More particularly it relates to an MIS transistor circuit which is operated alternately in a reset state or in an active state, the MIS transistor circuit having a voltage holding circuit integrated therein for preventing error operations due to variations of the power supply voltage.
2. Description of the Prior Art
Some types of MIS transistor circuits, for example, a dynamic MIS memory, can be operated alternately in a reset state or an active state. Such circuits are hereinafter referred to as dynamic MIS transistor circuits. In the reset state, the various operating points (nodes) in a dynamic MIS transistor circuit are charged or discharged to a predetermined potential level, whereby the dynamic MIS transistor circuit can perform a desired active operation in the active state.
During operation of the dynamic MIS transistor circuits, however, the power supply voltage often fluctuates due to external noise, or due to turning on or off of peripheral circuits, etc. Due to the fluctuations, the power supply voltage during the active period often differs from the power supply voltage during the preceeding reset period. This impedes the normal operation of the dynamic MIS transistor circuit, as hereinafter described in detail.